Memory circuit having improved sense-amplifier block and method for forming same

ABSTRACT

A memory circuit includes first and second amplifier stages that are respectively located within first and second regions of a semiconductor structure, and a memory array that is also located in the semiconductor structure. The memory circuit also includes a first set of digit lines that is coupled to the memory array, extends from the memory array into the first region, and is coupled to the first amplifier stage. The memory circuit further includes a second set of digit lines that is coupled to the memory array, extends from the memory array through the first region and into the second region, is coupled to the second amplifier stage, and is electrically isolated from the first amplifier stage.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No. 09/143,164, filed Aug. 28, 1998 now U.S. Pat. No. 6,111,773.

TECHNICAL FIELD

The invention relates generally to integrated circuits, and more particularly to a memory circuit having a sense-amplifier block that receives a large number of digit lines per given block width and a method for laying out the block.

BACKGROUND OF THE INVENTION

Today's memory designers continually strive to increase the data-storage density of memory arrays. FIG. 1 is a schematic diagram of a conventional memory circuit 8, which includes multiple memory-array sections 10 and 12 and sense-amplifier blocks 13. For clarity, only two array sections 10 and 12 are shown in FIG. 1. The array sections 10 and 12 each include memory cells 14, which each include an access transistor 16 and a storage capacitor 18. Each of the cells 14 is coupled to a respective word line 20, which is driven by a respective row decoder 22. Each cell 14 is also coupled to a respective digit line 24. The digit lines 24 are arranged in laterally spaced complementary (D and {overscore (D)}) pairs 15, each pair being alternately coupled to a respective one of the sense-amplifier blocks 13 on a different side of the respective array section 10 or 12. For example, one set of aligned digit-line pairs 15 a and 15 b in the array sections 10 and 12 are coupled to the same one of the sense-amplifier blocks 13 a, which is disposed between the array sections 10 and 12. Therefore, an adjacent digit-line pair 15 c in the array section 10 is coupled to a respective one of the sense-amplifier blocks 13 b, and an adjacent digit-line pair 15 d in the array section 12 is coupled to a respective one of the sense-amplifier blocks 13 c. (The sense-amplifier blocks 13 b and 13 c may also be coupled to additional respective array sections not shown in FIG. 1.) Although shown as receiving one digit-line pair 15 from each side, each of the blocks 13 may receive multiple digit-line pairs 15 from each side. The blocks 13 each include isolation circuits 27, which couple the selected array section 10 or 12 to sense amplifiers 11 during a read or write cycle.

Furthermore, each digit line 24 is coupled to the memory cells 14 in every other row of the respective array section 10 or 12. That is, one digit line 24 of respective digit-line pairs 15 is coupled to the memory cells 14 in a respective even row, and the other digit line 24 of the same digit-line pair 15 is coupled to the memory cells 14 in a respective odd row. This type of layout is known as a folded digit-line architecture, and is typically used to reduce the amount of noise on the digit lines 24. Because the circuit 8 is laid out according to a folded digit-line architecture, the memory cells 14 each occupy approximately 8 square feature sizes. (A feature size is the minimum dimension, such as a line or transistor gate width, realizable with the semiconductor process used to manufacture the circuit 8.)

Still referring to FIG. 1, in operation during a read or write cycle, one or more memory cells 14 within a selected one of the array sections 10 and 12 are addressed, and the isolation circuits 27 couple the digit lines 24 that are connected to the addressed memory cells 14 to the respective sense amplifiers 11 and isolate the digit lines 24 that are connected to the unaddressed memory cells 14 from the sense amplifiers 11. During a write cycle, data is coupled from a data bus to write drivers (both not shown in FIG. 1), which drive the data through an input/output circuit 34 onto the respective digit lines 24 and into the addressed memory cells 14. During a read cycle, the respective sense-amplifier blocks 13 couple data from the addressed memory cells 14 to the data bus through the input/output circuit 34.

FIG. 2 is a schematic block diagram of the sense-amplifier blocks 13, the array sections 10 and 12 and another array section 30, and the respective interfaces 31 therebetween. In this embodiment, each sense-amplifier block 13 receives four digit-line pairs 15 from each array section 10, 12, and includes pairs of complementary digit lines 32 that respectively correspond to the received pairs 15 of complementary digit lines 24. The isolation circuits 27 are coupled to the digit lines 24 of a respective array sections 10, 12, and 30 and to the digit lines 32. As discussed above in conjunction with FIG. 1, the respective isolation circuits 27 couple the digit lines 24 that are connected to the memory cells 14 to the digit lines 32 during a read or write cycle. Additionally, each block 13 includes a conventional input/output circuit 36, which couples the digit lines 32 to complementary I/O lines 38 during a read or a write cycle, and isolates the digit lines 32 from the I/O lines 38 otherwise. Each of the sense amplifiers 11 may also include conventional circuitry for equilibrating the digit lines 32 and the digit lines 24 before a read cycle. Each block 13 also includes a conventional PMOS sense-amplifier section 33, which includes pairs of PMOS transistors (not shown in FIG. 2) that are respectively coupled to the pairs of digit lines 32. Each block 13 further includes a conventional NMOS sense-amplifier section 34, which includes corresponding pairs of NMOS transistors (not shown in FIG. 2) that are also respectively coupled to the pairs of digit lines 32. The corresponding pairs of PMOS and NMOS transistors together form the respective sense amplifiers 11 (FIG. 1), one for each pair 15 of the digit lines 32.

Still referring to FIG. 2, the digit lines 24 emerge from the respective array sections 10, 12, and 30 in the same semiconductor layer and with a certain lateral spacing called the pitch. For example, the pitch between the digit lines 24 in the same pair 15 is a distance d1, and the pitch between adjacent digit lines 24 in different pairs 15 is a distance d2. In the illustrated embodiment, d2 is approximately 3 dl, although this ratio may be different for other array sections. The sense-amplifier blocks 13 are often constructed to receive the digit lines 24 in the same semiconductor layer and at the same pitch at which they emerge from the respective array section. Therefore, the blocks 13 are typically constructed so that along any one side of a respective array section, the sum of the respective widths w of all the blocks 13 adjacent to this array side are no more than the width W of the array. Thus, the array sections 10, 12, and 30 and the blocks 13 occupy the same total width so as to use the layout area of the circuit 8 in an efficient manner. This geometry inherently limits the number of digit lines 24, 32 that can extend through the array sections 10, 12, 30 and the blocks 13.

Referring to FIG. 3, one way to increase the data-storage density of a memory circuit is to layout the array sections according to a bi-level digit-line architecture. Generally, the density of an array section is limited by the lateral spacing of digit lines. In the bi-level architecture, the array sections include additional layers of digit lines stacked on top of each other. In such an architecture, bi-level digit lines 42 in the same complementary pair 43 are located in different semiconductor layers so that one digit line 42 of the pair 43 is disposed atop the other digit line 42 of the same pair 43. As the digit lines 42 emerge from the array section, however, the digit lines 42 of each pair 43 may be routed such that they are in the same semiconductor layer. This architecture allows the memory cells 14 (FIG. 1) to each have an area of approximately 6 square feature sizes instead of the approximately 8 square feature sizes required by each memory cell 14 in the folded-digit-line circuit 8 of FIG. 1. But, because the bi-level architecture allows an additional layer of digit lines 42 within a given area, the bi-level architecture also increases the density of the digit lines 42 in each array section. This bi-level digit-line architecture is discussed more in detail in “A Novel Architecture for Advanced High Density Dynamic Random Access Memories, A Thesis Presented in Partial Fulfillment of the Requirements for the Degree of Master of Science with a Major in Electrical Engineering in the College of Graduate Studies University of Idaho” by Brent Keeth (May 1996), which is incorporated by reference.

FIG. 4 is a proposed schematic block diagram of a memory circuit 41 that includes array sections 44 laid out according to a bi-level digit-line architecture and coupled to the sense-amplifier blocks 13. (Bi-level digit line architecture is an architecture that has been designed only recently, and a memory circuit using the bi-level architecture that includes sense-amplifier blocks has not yet been developed.) Referring to FIGS. 3 and 4, as they emerge from the side of the respective array 44, the digit lines 42 are routed with a tighter pitch than the laterally spaced digit lines 24 of FIG. 1. Additionally, the digit lines 42 are disposed in the same semiconductor layer as they emerge from the respective array section 44. So that the bi-level array section 44 can be constructed to have a width that is the same or smaller than the width W of the array sections 10, 12, and 30 of FIG. 2, the pitch d 3 between digit lines 42 of the same digit-line pair 43 is approximately the same as the pitch d 4 between adjacent digit lines 42 of different pairs 43. Typically, the pitches d 3 and d 4 are equal to the pitch d 1 of FIG. 1. Therefore, the array sections 44 each have a width that is approximately equal to the width W even though the array sections 44 each include twice the number of digit lines as each of the array sections 10, 12, and 30 of FIG. 2.

Still referring to FIG. 4, a problem with this layout is that it is difficult to use the sense-amplifier blocks 13 with the array sections 44. For example, because the array sections 44 each have twice the number of digit lines 42, the memory circuit 41 has twice as many sense-amplifier blocks 13. Therefore, the combined widths w of the sense-amplifier blocks 13 are equal to at least 2 W, which is at least twice as wide as the widths of the array sections 44. Therefore, the array sections 44 in a same column of array sections would be separated by respective areas having widths of at least W. Furthermore, because it would be difficult to form circuitry in these separation areas, these areas would significantly increase the overall area of the memory circuit 41, perhaps even by an amount greater than the area savings realized by the array sections 44 having the bi-level architecture. Additionally, as discussed above in conjunction with FIG. 2, the blocks 13 are constructed to receive digit lines at a pitch of d1 between digit lines of the same pair and at a pitch of d2 between adjacent digit lines of different pairs. Therefore, the digit lines 42 must be routed according to these pitches after they emerge from the array sections 44.

Although the above discussion focuses primarily on a bi-level architecture, similar problems would also be experienced with array sections 44 having more layers of digit lines 24 than two, such as a tri-level architecture. In fact, as each layer of digit lines 24 is added, the problem is worsened as the additional digit lines 24 require additional sense-amplifier blocks 13. Each additional sense-amplifier block 13 increases the width of the separation areas between the array sections 44, significantly increasing the overall area of the memory circuit 41. Similarly, this problem can exist for all types of layout configurations for array sections 44, such as open digit line and folded digit line architecture.

SUMMARY OF THE INVENTION

In one aspect of the present invention, a memory circuit includes first and second amplifier stages that are respectively located within first and second regions of a semiconductor structure, and a memory array that is also located in the semiconductor structure. The memory circuit also includes a first set of digit lines that is coupled to the memory array, extends from the memory array into the first region, and is coupled to the first amplifier stage. The memory circuit further includes a second set of digit lines that is coupled to the memory array, extends from the memory array through the first region and into the second region, is coupled to the second amplifier stage, and is electrically isolated from the first amplifier stage.

Such a memory circuit can incorporate bi-level array sections without large separation areas therebetween.

BRIEF DESCRIPTION OF THE DRAWINGS

The file of this patent contains at least one drawing executed in color. Copies of this patent with color drawing(s) will be provided to the Patent and Trademark Office upon request and payment of the necessary fee.

FIG. 1 is a schematic diagram of a portion of a conventional memory circuit.

FIG. 2 is a block diagram of the array sections and sense-amplifier blocks of the memory circuit of FIG. 1.

FIG. 3 is an isometric view of digit lines arranged according to a bi-level architecture.

FIG. 4 is a block diagram of a bi-level array section coupled to sense-amplifier blocks like the sense-amplifier blocks of FIG. 2.

FIG. 5A is an isometric block diagram of a memory circuit in accordance with one embodiment of the invention.

FIG. 5B is a top view of the memory circuit of FIG. 5A.

FIG. 5C is a cross section of one embodiment of a semiconductor structure in which the memory circuit of FIGS. 5A and 5B is disposed.

FIG. 6 is a layout diagram of one embodiment of the sense-amplifier block of FIGS. 5A, 5B, and 5C.

FIG. 7 is a schematic block diagram of the memory circuit of FIGS. 5A, 5B, and 5C.

FIG. 8 is a schematic block diagram of an electronic system that incorporates the memory circuit of FIG. 7.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 5A and 5B are respective isometric and top views of a memory circuit 50 according to an embodiment of the invention, and FIG. 5C is one embodiment of a cross section of a semiconductor structure in which the circuit 50 is so disposed.

The circuit 50 includes sense-amplifier blocks 52, which are disposed between and coupled to adjacent bi-level array sections 54. The array sections 54 are similar to the bi-level array sections 44 of FIG. 4. Digit lines 64 emerge from the sides of the array sections 54 at a pitch d 5. Each block 52 includes two semiconductor regions 56 a and 56 b and two sense-amplifier stages 58 a and 58 b respectively disposed therein. In one embodiment, each stage 58 a and 58 b is similar to a sense-amplifier block 13 of FIG. 2. Each block 52 also includes two sets 60 a and 60 b of digit lines 62. The set 60 a of digit lines 62 extends through the first region 56 a and is coupled to the first amplifier stage 58 a, and also extends through the second region 56 b and is electrically isolated from the second amplifier stage 58 b. Conversely, the set 60 b of digit lines 62 extends through the second region 56 b and is coupled to the second amplifier stage 58 b, and extends through the first region 56 a and is electrically isolated from the first amplifier stage 58 a. Thus, as described below, such routing of the digit lines 62 allows the block 52 to receive digit lines 64 at the same pitch d5 at which they emerge from their respective bi-level array section 54. This allows the combined widths of the blocks 52 to be no more than the width of the adjacent array sections 54, and thus allows the array sections 54 to be separated by areas that are significantly smaller than the separation areas of FIG. 4.

One effect of using the above described geometry is that the length of the sense-amplifier block is increased: typically doubled. This effect, however, is an acceptable tradeoff for increasing the overall density of circuitry for the memory device by placing circuitry in the formerly unusable space between the memory array sections 44 (as seen in FIG. 4), as described below.

Still referring to FIGS. 5A and 5B, each sense-amplifier stage 58 a and 58 b includes an NMOS sense-amplifier section 68, an input/output circuit 70, and a PMOS sense-amplifier section 72, which in one embodiment occupy respective regions having the same width and are constructed and operate similarly to the NMOS section 34, input/output section 36, and PMOS section 33, respectively, of FIG. 2. Isolation circuits 66 a, 66 b are coupled to the respective sense-amplifier stages 58 a, 58 b, and to the respective array sections 54 a, 54 b. In one embodiment, the isolation circuits 66 are constructed such that the digit lines 62 are at the pitch d5 and in the same semiconductor layer as they enter, pass through, and emerge from the isolation circuit 66. However, because of the sizes of the transistors (not shown) that compose the NMOS and PMOS sections 68 and 72 and the input/output circuit 70, these components can only receive and operate on some of the digit lines 62 if the respective regions they occupy are to have the same width as the region occupied by the isolation circuit 66. Therefore, as discussed below, two amplifier states 58 a and 58 b are used, one for each set 60 a and 60 b of the digit lines 62.

The digit lines 64 a emerge from the array section 54 a and enter the adjacent isolation circuit 66 a at the same pitch d5 and in the same semiconductor layer. (See below and FIG. 5C for a discussion of the semiconductor structure in which the memory circuit 50 is disposed.) During a read or write cycle, the isolation circuit 66 a couples the digit lines 64 a to the digit lines 62 when the array section 54 a is selected, and isolates the digit lines 64 a from the digit lines 62 when the array section 54 a is not selected.

After they emerge from the isolation circuit 66 a, the set 60 a of digit lines 62 are routed through the first semiconductor region 56 a such that they are electrically coupled to the NMOS amplifier section 68 a, the input/output circuit 70 a, and the PMOS amplifier section 72 a. Thus, during a read cycle, the first stage 58 a amplifies and couples the data signals carried from the array section 54 a by the first et 60 a of digit lines 62 to the data bus through the input/output circuit 70 a, and couples data signals from the data bus to the set 60 a of digit lines 62 through the input/output circuit 70 a during a write cycle.

Conversely, after they emerge from the isolation circuit 66 a, the set 60 b of digit lines 62 is routed through the first semiconductor region 56 a such that they are electrically isolated from the NMOS amplifier section 68 a, the input/output circuit 70 a, and the PMOS amplifier section 72 a. For example, the set 60 b of digit lines 62 may be routed in a semiconductor layer that is above the layers and the substrate portions in which these components of the amplifier stage 58 a are disposed. Or, the set 60 b of digit lines 62 may be routed through the substrate beneath these components. It is also possible for the set 60 b of digit lines 62 to be routed in the same layers in which the components of the amplifier stage 58 a are disposed while still maintaining electrical isolation from these components.

As the sets 60 a and 60 b of digit lines emerge from the first region 56 a into an intermediate region 74, they are routed in the semiconductor layers so as to facilitate electrical coupling of the set 60 b of digit lines 62 to the stage 58 b and to facilitate electrical isolation of the set 60 a of digit lines 62 from the stage 58 b. In one embodiment, the set 60 b is routed to lower ones of the semiconductor layers and the set 60 a is routed to upper ones of the semiconductor layers.

The sets 60 a and 60 b of digit lines 62 enter the region 56 a from the region 74. The set 60 b is routed through the regions occupied by and is electrically coupled to the PMOS section 72 b, the input/output circuit 70 b, and the NMOS section 68 b. Conversely, the set 60 a is routed past these components, either in semiconductor layers that are above the layers that these components occupy, or through the substrate below these components, such that the set 60 a is electrically isolated from the NMOS and PMOS sections 68 b, 72 b, and the input/output circuit 70 b. Again, the set 60 a may also be routed through the semiconductor layers that are occupied by the components while still maintaining electrical isolation from them. As the sets 60 a and 60 b approach the isolation circuit 66 b, they are routed to the same semiconductor layer such that they enter the circuit 66 b at the pitch d5 and are electrically coupled thereto. The digit lines 64 b also enter the isolation circuit 66 b at the pitch d5. During a read or write cycle, the circuit 66 b couples the digit lines 62 to the digit lines 64 b when the array section 54 b is selected, and isolate the digit lines 62 from the digit lines 64 b when the array section 54 b is not selected.

Therefore, by routing the digit lines 62 as discussed above, the amplifier stages 58 a and 58 b can be cascaded such that the combined widths of the sense-amplifier blocks 52 do not exceed the width of the adjacent array sections 54.

Although the embodiment of FIG. 5 shows sense-amplifier block 52 with four digit lines 64 emerging from the memory arrays 54 a and 54 b and entering the block 52, in a more general sense, the sense-amplifier block 52 may comprise N digit line pairs (each comprising two digit lines 64 a) from a first memory array, such as memory array 54 a, M sense-amplifier circuits 58 a in a first region 56 a, X digit lines pairs (each comprising two digit lines 64 b) from a second memory array, such as memory array 54 b, and Y sense-amplifier circuits 58 b in a second region 56 b.

The N digit-line pairs are coupled to the M sense-amplifier circuits 58 a, one digit-line pair per sense-amplifier circuit. Significantly, M is at most equal to N-1. Therefore, at least one of the N digit-line pairs is not coupled to one of the M sense-amplifier circuits instead. Instead, the digit line pairs that are not coupled to one of the M sense-amplifier circuits 58 a (equal to N-M) continue into the second region 56 b, and are coupled to respective ones of the Y sense-amplifier circuits 58 b, one digit-line pair per sense-amplifier circuit.

The X digit-line pairs are coupled to the Y sense-amplifier circuits 58 b, one digit-line pair per sense-amplifier circuit. Significantly, Y is at most equal to X-1. Therefore, at least one of the X digit-line pairs is not coupled to one of the Y sense-amplifier circuits. Instead, the digit line pairs that are not coupled to one of the Y sense-amplifier circuits 58 b (equal to X-Y) continue into the first region 56 a, and are coupled to respective ones of the M sense-amplifier circuits 58 a, one digit-line pair per sense-amplifier circuit.

Thus, because at least one digit-line pair from each set of digit lines N and X pass through one respective region 56 a, 56 b and into the other respective region 56 b, 56 a for amplification, additional digit lines (equal to N-M and X-Y) may be amplified within a given width as compared to conventional sense-amplifier layouts (as described above). In fact, N (or X) digit lines from a single memory array may be amplified within a region no wider than the regions 56 a and 56 b, with the width of the regions 56 a and 56 b typically being no wider than a width required by conventional sense-amplifier circuit layouts to amplify only {fraction (1/2+L )} N (or {fraction (1/2+L )} X) digit-line pairs (as discussed above).

FIG. 5C is a cross section of one embodiment of a semiconductor structure 73 in which the memory circuit 50 is formed. The structure 73 includes a semiconductor substrate 75 having layers 76, 77, 78, 79, 80, and 81 disposed thereon. The layers 76, 78, and 80 are dielectric layers, and the layers 77, 79, and 81 are conductive layers. There may be additional or fewer conductive and dielectric layers. Some of the circuit elements that make up the sense-amplifier block 52, such as transistors (not shown), that make up the NMOS and PMOS sections 68 and 72, may be partially or fully disposed within the substrate 75. The digit lines 60 (FIGS. 5A-5B) are routed in at least one of the conductive layers 77, 79, and 81, and may be electrically coupled to the circuit elements disposed in the substrate 75. The digit lines 60 may also be electrically isolated from the circuit elements within the substrate 75 by disposing at least one non-conductive layer between the digit lines and the circuit elements within the substrate 75. Thus, for example, within the region 56 a, the layers 77 or 79 may contain the digit lines 60 a, which are electrically coupled to the stage 58 a, some circuit elements of which are disposed in the substrate 75. Conversely, the digit lines 60 b, which are not coupled to the stage 58 a, may be routed through the conductive layer 81, which is electrically isolated from the substrate 75 and the digit lines 60 a by the dielectric layer 80. Similarly, the digit lines 60 a and 60 b may be respectively routed through layers 81 and 77 or 79 within the region 56 b so that the digit lines 60 b are electrically coupled to circuit elements of the stage 58 b and the digit lines 60 a are electrically isolated from these circuit elements and the digit lines 60 b.

FIG. 6 is a layout diagram of one embodiment of the sense-amplifier block 52 of FIGS. 5A, 5B and 5C. In this embodiment, the NMOS sections 68 a and 68 b each include four transistor pairs 82 a and 82 b, respectively. The transistor pairs 82 a are coupled to respective complementary pairs of digit lines 62 from the set 60 a, and the transistor pairs 82 b are coupled to respective complementary pairs of digit lines 62 from the set 60 b. Likewise, the PMOS sections 72 a and 72 b each include four transistor pairs 84 a and 84 b, respectively. The transistor pairs 84 a are coupled to respective complementary pairs of digit lines 62 from the set 60 a, and the transistor pairs 84 b are coupled to respective complementary pairs of digit lines 62 from the set 60 b. At least one data-line pair 60 b passes through the semiconductor region 56 a electrically isolated from the first amplifier stage 58 a and is coupled to the second amplifier stage 58 b. Similarly, at least one data-line pair 60 a is coupled to the first amplifier stage 58 a and passed through the second amplifier stage 58 b, electrically isolated from the second amplifier stage 58 b.

FIG. 7 is a schematic block diagram of one embodiment of the memory circuit 50 of FIGS. 5A, 5B, and 5C. The memory circuit 50 includes an address register 132, which receives an address from an ADDRESS bus. A control logic circuit 134 receives a clock (clk) signal, and receives clock enable (CKE), chip select ({overscore (CS)}), row address strobe ({overscore (RAS)}), column address strobe ({overscore (CAS)}) and write enable ({overscore (WE)}) signals from a COMMAND bus, and communicates with the other circuits of the memory circuit 50. A row address multiplexer 136 receives the address signal from the address register 132 and provides the row address to the row-address latch-and-decode circuits 138 a and 138 b for the memory bank 140 a or 140 b, respectively. During read and write cycles, the row-address latch-and-decode circuits 138 a and 138 b activate word lines of the addressed rows of memory cells in the memory banks 140 a and 140 b, respectively. Read/write circuits 142 a and 142 b read data from the addressed memory cells in the memory banks 140 a and 140 b, respectively, during a read cycle, and write data to the addressed memory cells during a write cycle. The read/write circuits 142 a, 142 b include the sense-amplifier block 52 of FIGS. 5A, 5B, and 5C. The memory banks 140 a, 140 b include the array sections 54 a and 54 b, respectively, of FIGS. 5A, 5B, and 5C. A column-address latch-and-decode circuit 144 receives the address from the address register 132 and provides the column address of the selected memory cells to the read/write circuits 142 a and 142 b. For clarity, the address register 132, the row-address multiplexer 136, the row-address latch-and-decode circuits 138 a and 138 b, and the column-address latch-and-decode circuit 144 can be collectively referred to as an address decoder.

A data input/output (I/O) circuit 146 includes a plurality of input buffers 148. During a write cycle, the buffers 148 receive and store data from the external DATA bus, and the read/write circuits 142 a and 142 b provide the stored data to the memory banks 140 a and 140 b, respectively. The data I/O circuit 146 also includes a plurality of output drivers 150. During a read cycle, the read/write circuits 142 a and 142 b provide data from the memory banks 140 a and 140 b, respectively, to the drivers 150, which in turn provide this data to the DATA bus.

A refresh counter 152 stores the address of the row of memory cells to be refreshed either during conventional auto-refresh mode or self-refresh mode. After the row is refreshed, a refresh controller 154 updates the address in the refresh counter 152, typically by either incrementing or decrementing the contents of the refresh counter 152 by one. Although shown separately, the refresh controller 154 may be part of the control logic 134 in other embodiments of the memory device 130.

The memory circuit 50 may also include an optional charge pump 156, which steps up the power-supply voltage V_(DD) to a voltage V_(DDP). In one embodiment, the pump 156 generates V_(DDP) approximately 1-1.5 V higher than V_(DD). The memory circuit 130 may also use V_(DDP) to conventionally overdrive selected internal transistors.

FIG. 8 is a block diagram of an electronic system 160, such as a computer system, that incorporates the memory circuit 50 of FIG. 7. The system 160 includes computer circuitry 162 for performing computer functions, such as executing software to perform desired calculations and tasks. The circuitry 162 typically includes a processor 164 and the memory circuit 50, which is coupled to the processor 164. One or more input devices 166, such as a keyboard or a mouse, are coupled to the computer circuitry 162 and allow an operator (not shown) to manually input data thereto. One or more output devices 168 are coupled to the computer circuitry 162 to provide to the operator data generated by the computer circuitry 162. Examples of such output devices 168 include a printer and a video display unit. One or more data-storage devices 170 are coupled to the computer circuitry 162 to store data on or retrieve data from external storage media (not shown). Examples of the storage devices 170 and the corresponding storage media include drives that accept hard and floppy disks, tape cassettes, and compact disk read-only memories (CD-ROMs). Typically, the computer circuitry 162 includes address data and command buses and a clock line that are respectively coupled to the ADDRESS, DATA, and COMMAND buses, and the CLK line of the memory device 50.

From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims. 

What is claimed is:
 1. A sense-amplifier block for a memory device having a bi-level architecture memory array and first, second and third conductive layers, the sense-amplifier block comprising: N digit line pairs coupled to and passing through and out of the sense-amplifier block: M sense-amplifier circuits disposed in a first region and coupled to the N digit line pairs through first and second conductive layers, M being no more than N-1, each of the M sense-amplifier circuits coupled to no more than one of the N digit line pairs; X digit line pairs coupled to and passing through and out of the sense-amplifier block; Y sense-amplifier circuits disposed in a second region and coupled to the X digit line pairs through the first and second conductive layers, Y being no more than X-1, each of the Y sense-amplifier circuits coupled to no more than one of the X digit line pairs; N-M of the N digit line pairs being electrically isolated from the M sense-amplifier circuits and respectively coupled to the Y sense-amplifier circuits through a third conductive layer isolated from the first and second conductive layers; and X-Y of the X digit line pairs being electrically isolated from the Y sense-amplifier circuits and respectively coupled to the M sense-amplifier circuits through the third conductive layer.
 2. The sense-amplifier block of claim 1 wherein the N digit line pairs that are coupled to the M sense-amplifier circuits traverse the first region through the first and second conductive layers and the N-M of the N digit line pairs that are not coupled to the N-1 sense-amplifier circuits traverse the first region through the third conductive layer.
 3. The sense-amplifier block of claim 2 wherein the first and second conductive layers are isolated from each other by a dielectric layer disposed therebetween.
 4. The sense-amplifier block of claim 1 wherein the X digit line pairs that are coupled to the Y sense-amplifier circuits traverse the second region through the first and second conductive layers and the X-Y of the X digit line pairs that are not coupled to the Y sense-amplifier circuits traverse the second region through the third conductive layer.
 5. The sense-amplifier block of claim 4 wherein the first and second conductive layers are isolated from each other by a dielectric layer disposed therebetween.
 6. The sense-amplifier block of claim 1 wherein the N digit line pairs are formed from the same conductive layer at a point where the N digit line pairs are coupled to the sense-amplifier block.
 7. The sense-amplifier block of claim 1 wherein the X digit line pairs are formed from the same conductive layer at a point where the X digit line pairs are coupled to the sense-amplifier block.
 8. An array of sense-amplifiers, comprising: M sense-amplifier circuits disposed in a first region; Y sense-amplifier circuits disposed in a second region; N digit line pairs traversing the first and second regions and coupled to a respective one of the M sense amplifier circuits, the N digit lines formed from first and second conductive layers to traverse the first region and formed from a third conductive layer to traverse the second region; and X digit line pairs traversing the first and second regions and coupled to a respective one of the Y sense amplifier circuits, the X digit lines formed from the first and second conductive layers to traverse the second region and formed from the third conductive layer to traverse the first region.
 9. The array of sense-amplifiers of claim 8 further coupled to first and second memory arrays having digit lines arranged in a bi-level architecture, the first array coupled to the N and X digit line pairs and the second array coupled to the X and N digit line pairs.
 10. The array of sense-amplifiers of claim 8 wherein the M and Y amplifiers are formed substantially in line in the first and second regions, respectively.
 11. The array of sense-amplifiers of claim 8 wherein the first and second conductive layers are formed above the third layer.
 12. The array of sense-amplifiers of claim 8 wherein the third layer is formed above the first and second conductive layers.
 13. The array of sense amplifiers of claim 8 wherein the third layer is formed between the first and second conductive layers.
 14. The array of sense amplifiers of claim 8 wherein the N digit lines pairs are formed alternating with the X digit lines pairs.
 15. The array of sense amplifiers of claim 8, further comprising a first isolation circuit coupled to a first end of the N and X digit line pairs and a second isolation circuit coupled to an opposite end of the N and X digit lines pairs to selectively couple a first and second memory array, respectively, to the N and X digit line pairs.
 16. A memory device, comprising: an amplifier circuit having first and second amplifier stages formed in first and second regions, respectively; and first and second memory arrays each having pairs of digit lines arranged in a bi-level digit line architecture, at least one of the pairs of digit lines of the first memory array coupled to the first amplifier stage through first and second conductive layers and at least another one of the pairs of digit lines of the first memory array coupled to the second amplifier stage through a third conductive layer, and at least one of the pairs of digit lines of the second memory array coupled to the second amplifier stage through first and second conductive layers and at least another one of the pairs of digit lines of the second memory array coupled to the first amplifier stage through a third conductive layer.
 17. The memory device of claim 16, further comprising a first isolation circuit coupled between the pairs of digit lines of the first memory array and the first and second amplifier stages and a second isolation circuit coupled between the pairs of digit lines of the second memory array and the first and second amplifier stages, the isolation circuits to selectively couple the pairs of digit lines of the respective memory arrays to the first and second amplifier stages.
 18. The memory device of claim 16 wherein the first and second amplifier stages are formed in the first and second regions substantially in line.
 19. The memory device of claim 16 wherein the first and second conductive layers are formed above the third layer.
 20. The memory device of claim 16 wherein the third layer is formed above the first and second conductive layers.
 21. The memory device of claim 16 wherein the third layer is formed between the first and second conductive layers.
 22. The memory device of claim 16 wherein the first and second amplifier stages comprise a plurality of a sense amplifiers, each including first and second cross coupled CMOS inverters.
 23. The memory device of claim 22, further comprising input-output (I/O) lines coupled to outputs of the sense amplifiers.
 24. The computer system of claim 16 wherein the first and second amplifier stages of the memory device comprise a plurality of a sense amplifiers, each including first and second cross coupled CMOS inverters.
 25. A computer system, comprising: a data input device; a data output device; processing circuitry coupled to the data input and data output devices; and a memory circuit coupled to the processing circuitry and having a bi-level architecture memory array formed with first, second and third conductive layers, the memory circuit comprising: an amplifier circuit having first and second amplifier stages formed in first and second regions, respectively; and first and second memory arrays each having pairs of digit lines arranged in a bi-level digit line architecture, at least one of the pairs of digit lines of the first memory array coupled to the first amplifier stage through first and second conductive layers and at least another one of the pairs of digit lines of the first memory array coupled to the second amplifier stage through a third conductive layer, and at least one of the pairs of digit lines of the second memory array coupled to the second amplifier stage through first and second conductive layers and at least another one of the pairs of digit lines of the second memory array coupled to the first amplifier stage through a third conductive layer.
 26. The computer system of claim 25 wherein the memory device further comprises a first isolation circuit coupled between the pairs of digit lines of the first memory array and the first and second amplifier stages and a second isolation circuit coupled between the pairs of digit lines of the second memory array and the first and second amplifier stages, the isolation circuits to selectively couple the pairs of digit lines of the respective memory arrays to the first and second amplifier stages.
 27. The computer system of claim 25 wherein the first and second amplifier stages of the memory device are formed in the first and second regions substantially in line.
 28. The computer system of claim 25 wherein the first and second conductive layers are formed above the third layer.
 29. The computer system of claim 25 wherein the third layer is formed above the first and second conductive layers.
 30. The computer system of claim 25 wherein the third layer is formed between the first and second conductive layers.
 31. A method of accessing memory arrays having pairs digit lines arranged in a bi-level digit line architecture, the memory arrays included in a memory device having first, second and third conductive layers, the method comprising: when accessing a first array, coupling at least one pair of digit lines of the first array to a first sense amplifier stage through the first and second conductive layers and at least one other pair of digit lines of the first array to a second amplifier stage through the third conductive layer; and when accessing a second array, coupling at least one pair of digit lines of the second array to the second sense amplifier stage through the first and second conductive layers and at least one other pair of digit lines of the second array to a first amplifier stage through the third conductive layer.
 32. The method of claim 31, further comprising isolating the first array from the first and second sense amplifier stages when accessing the second array and isolating the second array from the first and second sense amplifier stages when accessing the first array.
 33. A method of accessing a memory array in a memory device having first and second amplifier stages formed in first and second regions, respectively, the method comprising coupling a first memory array to a first set of digit line pairs traversing the first and second regions and coupled to the first amplifier stage and coupling the first memory array to a second set of digit line pairs traversing the first and second regions and coupled to the second amplifier stage.
 34. The method of claim 33, further comprising isolating the first memory array from the first and second sets of digit line pairs and coupling a second memory array to the first and second digit line pairs when accessing the second memory array. 